In the prior general purpose data processing machines, as for example, the System 360 and System 370 series of processors produced by the assignee of this patent application, instruction words were used in at least three lengths of one, two, or three half words depending upon the number of operands to be fetched or returned to main storage and each function to be performed was set out in a different instruction, depending upon whether the operands were to be found in two general purpose registers, one register and one address in main storage or two addresses in main storage. Such an instruction set required a large decoding section for the functions and a lot of duplication of gating circuits to control the data paths within the processor.
In the disclosed embodiment of a data processor, a single general purpose format is used for an instruction and such an instruction will be good for any combination of register or storage locations for the operands to be processed. Likewise, there need be only one set of operand address decoding devices for, at least, the major part of the instruction set and new processor functions may be built into the processor with the addition of only the function decoder and its associated connections to the circuit gates. The inclusion of a third operand section in the instruction also enables the single instruction to control the performance of functions heretofore requiring a plurality of instructions or some not normally available at all in a general purpose processor.